DPACI ANNOUNCES QML-FSC 5962 MEMORY LINE

DPA Components International (DPACI) announces the introduction of the first family of Standard Microcircuit Drawings (SMDs) for Static Random Access Memory (SRAM) devices designed to support the availability of full Military (-55C to +125C, hermetically packaged) memory devices for mission critical applications. These devices are in full compliance with Defense Supply Center Columbus (DSCC) SMD’s.

This first family of Asynchronous SRAM products has memory sizes from 2MB to 16MB and is manufactured, tested and qualified by DPACI, a 30 year veteran provider of high reliability parts to the Military and Space industry. These devices contain a Cypress Semiconductor monolithic memory die and are offered in a 44-pin and 54-pin TSOP hermetic package custom designed to drop in the footprint of the plastic version.

Augmenting the first family of Asynchronous SRAM is the Synchronous SRAM family with memory sizes from 4 MB to 72 MB in high reliability plastic packages qualified to the Class N requirements as a COTS replacement turn-key solution to the military industry in SMD products. These devices will be tested and qualified over -55C to +125C with full read and record, CSAM and serialization traceability to prevent counterfeits, processing “above and beyond” MIL-PRF-38535 Class N requirements to increase the reliability of DPACI Class N products for mission critical applications.

DPACI, an ISO 9001:2008, AS9100 and DSCC certified manufacturing and test facility will provide these devices to the stringent requirements of MIL-PRF-38535 Class and N DSCC approved production lines located at Simi Valley, California, USA.

The use of available SMD devices as the order of precedence over Non-Standard devices and COTS is required per MIL-STD-3018, Parts Management Military Standard for all new designs or modified equipment. Defense Contractors with DoD or NASA Contracts calling out MIL-STD-3018 requirements starting 2009 shall investigate the use of these SMD memory devices prior to selecting their Non-Standard or COTS memory devices for final design.

Class N Synchronous family will be available in last quarter of 2009, Class V Asynchronous scheduled in 2nd quarter of 2010.